Implementation

Makefile integration via  cargo build

bindgen for FFI bindings

arrayVec for RAM allocation

The RTX_2000 simulator from Phil Koopman has the instruction decoding logic. It also nicely integrates the zero-cycle “;” word.

Use Rust’s “no-std” feature flag. After all, this is an embedded system. SIMH provides virtual file I/O, debugging support, virtual console, virtual display.

See if instruction decoding can be accomplished via Rust’s enum type.

Rust’s Borrow Checker will verify memory read/write access.

Rust’s array slices should be useful.

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You fill in sim_instr do the instruction decoding and execution.
sim_load will typically take some input file and put it in memory.
cpu_reg should contain all machine state.
parse_sym/fprint_sym is to assemble (with DEPOSIT) and disassemble (EXAMINE-M) instructions.
sim_devices is an array of DEVICE * for peripherals. Something like
build_dev_tab will go through the array and initialize data structures
at run time.
Refer to this: simh doc
Make use of asynchronous events. sim_activate posts a future event.
The “svc” routine will be called.

sub/readme.txt

parse_sym invokes Forth interpreter
print_sym invokes Forth disassembler

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Build with SIM_ASYNCH_IO=0

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