6-Nov
- Upgrade to Ventura since last update. Seems slower.
- Instruction decoding and execution works.
COLDworks. The strange RAM effective address shift right was due to the original hardware that ran Turbo C.intwas only 8 bits. The machine it’s simulating is 16 bits. The RTX2000 simulator used byte access to simulate the RTX2001A 21 bit hardware. HEXIN.Cnow generates arom.iniforsimh
COLD is partly defined as
{ : COLD? } ( - flag \ true is cold, 0 is warm)COLD @ 12345 12347 WITHIN NOT IF ( random)12345 COLD ! -1 EXIT ( is cold)THEN
where { and } store HEAD in the build machine dictionary, BODY to be stored in the target machine RAM space.
DBG(0)> CPU MEBR: 0x175D seg:addr=0:0x0 addr=0x0DBG(0)> CPU CPU: CALL 0:0x2EBA // Cold boot addressDBG(0)> CPU ASBR: PC=0x0DBG(0)> CPU ASBW: SPR: RSP=^0x1 PSP=0x0DBG(0)> CPU RSBW: RSB: I=^0x3F IPR=0x0DBG(0)> CPU ASBW: I=0x0DBG(0)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0DBG(0)> CPU ASBW: IPR: IPR=0x0DBG(0)> CPU ASBW: PC=0x2EBA // COLD variable bodyDBG(1)> CPU MEBR: 0x15E8 seg:addr=0:0x2EBA addr=0x2EBADBG(1)> CPU CPU: CALL 0:0x2BD0 // @ bodyDBG(1)> CPU ASBR: PC=0x2EBADBG(1)> CPU ASBW: SPR: RSP=^0x2 PSP=0x0DBG(1)> CPU RSBW: RSB: I=_0x0 IPR=0x0DBG(1)> CPU ASBW: I=0x2EBADBG(1)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0DBG(1)> CPU ASBW: IPR: IPR=0x0DBG(1)> CPU ASBW: PC=0x2BD0DBG(2)> CPU MEBR: 0x7D seg:addr=0:0x2BD0 addr=0x2BD0DBG(2)> CPU CPU: CALL 0:0xFA // LIT bodyDBG(2)> CPU ASBR: PC=0x2BD0DBG(2)> CPU ASBW: SPR: RSP=^0x3 PSP=0x0DBG(2)> CPU RSBW: RSB: I=^0x3A IPR=0x0DBG(2)> CPU ASBW: I=0x2BD0DBG(2)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0DBG(2)> CPU ASBW: IPR: IPR=0x0DBG(2)> CPU ASBW: PC=0xFADBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFADBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFADBG(3)> CPU CPU: LIT 56864 // LIT constant from RAMDBG(3)> CPU ASBR: SPR: RSP=0x3 PSP=0x0DBG(3)> CPU ASBW: SPR: RSP=0x3 PSP=^0x1DBG(3)> CPU PSBW: PSB=0xFFFFDBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFADBG(3)> CPU ASBW: CPR=0x0DBG(3)> CPU ASBW: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0DBG(3)> CPU ASBW: PC=0x2BD0DBG(3)> CPU RSBR: RSB: I=0x3A IPR=0x0DBG(3)> CPU ASBW: IPR: IPR=0x0DBG(3)> CPU ASBW: I=0x3ADBG(3)> CPU ASBW: SPR: RSP=_0x2 PSP=0x1DBG(3)> CPU MEBR: 0xEE00 seg:addr=0:0x2BD2 addr=0x2BD2 // UCODE @DBG(3)> CPU ASBW: PC=0x2BD2DBG(3)> CPU MEBR: 0xEE00 seg:addr=0:0x2BD2 addr=0x2BD2DBG(3)> CPU CPU: 2nd LIT 60928 // Memory bus access is a 2-cycle instructionDBG(3)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4DBG(3)> CPU ASBW: PC=0x2BD4DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4DBG(4)> CPU CPU: LIT 56832 // 2nd LIT constant from RAMDBG(4)> CPU ASBR: SPR: RSP=0x2 PSP=0x1DBG(4)> CPU ASBW: SPR: RSP=0x2 PSP=^0x2DBG(4)> CPU PSBW: PSB=0x0DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4DBG(4)> CPU MEBR: 0x3039 seg:addr=0:0x2BD6 addr=0x2BD6DBG(4)> CPU ASBW: PC=0x2BD6DBG(4)> CPU MEBR: 0x3039 seg:addr=0:0x2BD6 addr=0x2BD6DBG(4)> CPU CPU: 2nd LIT 12345DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8DBG(4)> CPU ASBW: PC=0x2BD8DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8DBG(5)> CPU CPU: LIT 56832 // Memory bus access is a 2-cycle instructionDBG(5)> CPU ASBR: SPR: RSP=0x2 PSP=0x2DBG(5)> CPU ASBW: SPR: RSP=0x2 PSP=^0x3DBG(5)> CPU PSBW: PSB=0xDE20DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8DBG(5)> CPU MEBR: 0x303B seg:addr=0:0x2BDA addr=0x2BDADBG(5)> CPU ASBW: PC=0x2BDADBG(5)> CPU MEBR: 0x303B seg:addr=0:0x2BDA addr=0x2BDADBG(5)> CPU CPU: 2nd LIT 12347DBG(5)> CPU MEBR: 0x177 seg:addr=0:0x2BDC addr=0x2BDCDBG(5)> CPU ASBW: PC=0x2BDCDBG(6)> CPU MEBR: 0x177 seg:addr=0:0x2BDC addr=0x2BDCDBG(6)> CPU CPU: CALL 0:0x2EEDBG(6)> CPU ASBR: PC=0x2BDCDBG(6)> CPU ASBW: SPR: RSP=^0x3 PSP=0x3DBG(6)> CPU RSBW: RSB: I=^0x3A IPR=0x0DBG(6)> CPU ASBW: I=0x2BDCDBG(6)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0DBG(6)> CPU ASBW: IPR: IPR=0x0DBG(6)> CPU ASBW: PC=0x2EEDBG(7)> CPU MEBR: 0xAEC0 seg:addr=0:0x2EE addr=0x2EEDBG(7)> CPU CPU: OVERDBG(7)> CPU ASBR: SPR: RSP=0x3 PSP=0x3DBG(7)> CPU ASBW: SPR: RSP=0x3 PSP=^0x4DBG(7)> CPU PSBW: PSB=0xDE00DBG(7)> CPU MEBR: 0xAC40 seg:addr=0:0x2F0 addr=0x2F0DBG(7)> CPU ASBW: PC=0x2F0
Simulation stopped, PC: 02F0 (0xAC40)
sim>
-----------------------
11-Sep
TDD. Gotta love it.
gcc -std=c99 -U__STRICT_ANSI__ -O2 -fno-strict-overflow -finline-functions -DSIM_GIT_COMMIT_ID=24260f06131f25688f758e22c1b49e72f8f2e8f2+uncommitted-changes -DSIM_GIT_COMMIT_TIME=2022-08-04T16:46:56+0100 -DSIM_COMPILER="Apple clang version 13.1.6" -DSIM_BUILD_TOOL=simh-makefile -I . -D_GNU_SOURCE -I/opt/local/include -DUSE_READER_THREAD -DSIM_ASYNCH_IO -DHAVE_PCRE_H -DHAVE_SYS_IOCTL -DSIM_HAVE_DLOPEN=dylib -DHAVE_UTIME -DHAVE_LIBPNG -DHAVE_ZLIB -DHAVE_GLOB -DHAVE_SHM_OPEN -I../Unity/src/ -I./RTX2001A/src/ \
./RTX2001A/test/test_mb.c ./RTX2001A/test/scp_stub.c ../Unity/src/unity.c \
-L/opt/local/lib -lpthread -lpcre -L/opt/local/lib/ -lpng -lz \
./RTX2001A/rtx2001a.a \
-o BIN/test_mb
$ ./BIN/test_mb
./RTX2001A/test/test_mb.c:55:test_long_store_00:FAIL: Expected 0 Was 64
-----------------------
1 Tests 1 Failures 0 Ignored
FAIL
mb is Memory Bus scp_stub.c is scp without main()
Building on Unity unit testing framework.
FFI integration proceeding apace. This means that the Rust bindgen tool has digested simh/sim_defs.h
Running /Users/jeffreychimene/git/SIM2001A/target/debug/deps/SIM2001A-8257d75b9163b925
running 101 tests
test bindgen_test_layout_BITFIELD … ok
<…>
test tests::it_works … ok
20-Aug
So no-stdbindgen is out. Turns out bindgen relies on std:: for its work. Rethinking the integration piece
20-Aug
Integration with simh looks like it will confined to using the FFI to call into Rust from the simh public API.
This is the time to thank Phil Koopman, PJK, for his trailblazing work documenting the RTX2001A. This project would not be possible without his work on the RTX2000 simulator.
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