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simh

Status

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6-Nov

  • Upgrade to Ventura since last update. Seems slower.
  • Instruction decoding and execution works. COLD works. The strange RAM effective address shift right was due to the original hardware that ran Turbo C. int was only 8 bits. The machine it’s simulating is 16 bits. The RTX2000 simulator used byte access to simulate the RTX2001A 21 bit hardware.
  • HEXIN.C now generates a rom.ini for simh

COLD is partly defined as

{ : COLD? } ( - flag \ true is cold, 0 is warm)
COLD @ 12345 12347 WITHIN NOT IF ( random)
12345 COLD ! -1 EXIT ( is cold)
THEN

where { and } store HEAD in the build machine dictionary, BODY to be stored in the target machine RAM space.

 

DBG(0)> CPU MEBR: 0x175D seg:addr=0:0x0 addr=0x0
DBG(0)> CPU CPU: CALL 0:0x2EBA                          // Cold boot address
DBG(0)> CPU ASBR: PC=0x0
DBG(0)> CPU ASBW: SPR: RSP=^0x1 PSP=0x0 
DBG(0)> CPU RSBW: RSB: I=^0x3F IPR=0x0 
DBG(0)> CPU ASBW: I=0x0
DBG(0)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0 
DBG(0)> CPU ASBW: IPR: IPR=0x0 
DBG(0)> CPU ASBW: PC=0x2EBA                             // COLD variable body
DBG(1)> CPU MEBR: 0x15E8 seg:addr=0:0x2EBA addr=0x2EBA
DBG(1)> CPU CPU: CALL 0:0x2BD0                          // @ body
DBG(1)> CPU ASBR: PC=0x2EBA
DBG(1)> CPU ASBW: SPR: RSP=^0x2 PSP=0x0 
DBG(1)> CPU RSBW: RSB: I=_0x0 IPR=0x0 
DBG(1)> CPU ASBW: I=0x2EBA
DBG(1)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0 
DBG(1)> CPU ASBW: IPR: IPR=0x0 
DBG(1)> CPU ASBW: PC=0x2BD0
DBG(2)> CPU MEBR: 0x7D seg:addr=0:0x2BD0 addr=0x2BD0
DBG(2)> CPU CPU: CALL 0:0xFA                            // LIT body
DBG(2)> CPU ASBR: PC=0x2BD0
DBG(2)> CPU ASBW: SPR: RSP=^0x3 PSP=0x0 
DBG(2)> CPU RSBW: RSB: I=^0x3A IPR=0x0 
DBG(2)> CPU ASBW: I=0x2BD0
DBG(2)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0 
DBG(2)> CPU ASBW: IPR: IPR=0x0 
DBG(2)> CPU ASBW: PC=0xFA
DBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFA
DBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFA
DBG(3)> CPU CPU: LIT 56864                              // LIT constant from RAM
DBG(3)> CPU ASBR: SPR: RSP=0x3 PSP=0x0 
DBG(3)> CPU ASBW: SPR: RSP=0x3 PSP=^0x1 
DBG(3)> CPU PSBW: PSB=0xFFFF
DBG(3)> CPU MEBR: 0xDE20 seg:addr=0:0xFA addr=0xFA
DBG(3)> CPU ASBW: CPR=0x0
DBG(3)> CPU ASBW: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0 
DBG(3)> CPU ASBW: PC=0x2BD0
DBG(3)> CPU RSBR: RSB: I=0x3A IPR=0x0 
DBG(3)> CPU ASBW: IPR: IPR=0x0 
DBG(3)> CPU ASBW: I=0x3A
DBG(3)> CPU ASBW: SPR: RSP=_0x2 PSP=0x1 
DBG(3)> CPU MEBR: 0xEE00 seg:addr=0:0x2BD2 addr=0x2BD2    // UCODE @
DBG(3)> CPU ASBW: PC=0x2BD2
DBG(3)> CPU MEBR: 0xEE00 seg:addr=0:0x2BD2 addr=0x2BD2
DBG(3)> CPU CPU: 2nd LIT 60928                          // Memory bus access is a 2-cycle instruction 
DBG(3)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4
DBG(3)> CPU ASBW: PC=0x2BD4
DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4
DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4
DBG(4)> CPU CPU: LIT 56832                              // 2nd LIT constant from RAM 
DBG(4)> CPU ASBR: SPR: RSP=0x2 PSP=0x1 
DBG(4)> CPU ASBW: SPR: RSP=0x2 PSP=^0x2 
DBG(4)> CPU PSBW: PSB=0x0
DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD4 addr=0x2BD4
DBG(4)> CPU MEBR: 0x3039 seg:addr=0:0x2BD6 addr=0x2BD6
DBG(4)> CPU ASBW: PC=0x2BD6
DBG(4)> CPU MEBR: 0x3039 seg:addr=0:0x2BD6 addr=0x2BD6
DBG(4)> CPU CPU: 2nd LIT 12345 
DBG(4)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8
DBG(4)> CPU ASBW: PC=0x2BD8
DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8
DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8
DBG(5)> CPU CPU: LIT 56832                               // Memory bus access is a 2-cycle instruction  
DBG(5)> CPU ASBR: SPR: RSP=0x2 PSP=0x2 
DBG(5)> CPU ASBW: SPR: RSP=0x2 PSP=^0x3 
DBG(5)> CPU PSBW: PSB=0xDE20
DBG(5)> CPU MEBR: 0xDE00 seg:addr=0:0x2BD8 addr=0x2BD8
DBG(5)> CPU MEBR: 0x303B seg:addr=0:0x2BDA addr=0x2BDA
DBG(5)> CPU ASBW: PC=0x2BDA
DBG(5)> CPU MEBR: 0x303B seg:addr=0:0x2BDA addr=0x2BDA
DBG(5)> CPU CPU: 2nd LIT 12347 
DBG(5)> CPU MEBR: 0x177 seg:addr=0:0x2BDC addr=0x2BDC
DBG(5)> CPU ASBW: PC=0x2BDC
DBG(6)> CPU MEBR: 0x177 seg:addr=0:0x2BDC addr=0x2BDC
DBG(6)> CPU CPU: CALL 0:0x2EE
DBG(6)> CPU ASBR: PC=0x2BDC
DBG(6)> CPU ASBW: SPR: RSP=^0x3 PSP=0x3 
DBG(6)> CPU RSBW: RSB: I=^0x3A IPR=0x0 
DBG(6)> CPU ASBW: I=0x2BDC
DBG(6)> CPU ASBR: IBC: IVB=0x0 TC=0x0 CYCEXT0 DPRSEL0 RSV0 PSV0 RSU0 PSU0 SEF0 
DBG(6)> CPU ASBW: IPR: IPR=0x0 
DBG(6)> CPU ASBW: PC=0x2EE
DBG(7)> CPU MEBR: 0xAEC0 seg:addr=0:0x2EE addr=0x2EE
DBG(7)> CPU CPU: OVER 
DBG(7)> CPU ASBR: SPR: RSP=0x3 PSP=0x3 
DBG(7)> CPU ASBW: SPR: RSP=0x3 PSP=^0x4 
DBG(7)> CPU PSBW: PSB=0xDE00
DBG(7)> CPU MEBR: 0xAC40 seg:addr=0:0x2F0 addr=0x2F0
DBG(7)> CPU ASBW: PC=0x2F0

Simulation stopped, PC: 02F0 (0xAC40)
sim>

 

-----------------------

11-Sep

TDD. Gotta love it.

gcc -std=c99 -U__STRICT_ANSI__  -O2 -fno-strict-overflow -finline-functions -DSIM_GIT_COMMIT_ID=24260f06131f25688f758e22c1b49e72f8f2e8f2+uncommitted-changes -DSIM_GIT_COMMIT_TIME=2022-08-04T16:46:56+0100  -DSIM_COMPILER="Apple clang version 13.1.6" -DSIM_BUILD_TOOL=simh-makefile -I . -D_GNU_SOURCE -I/opt/local/include -DUSE_READER_THREAD -DSIM_ASYNCH_IO -DHAVE_PCRE_H -DHAVE_SYS_IOCTL -DSIM_HAVE_DLOPEN=dylib -DHAVE_UTIME -DHAVE_LIBPNG -DHAVE_ZLIB -DHAVE_GLOB -DHAVE_SHM_OPEN  -I../Unity/src/ -I./RTX2001A/src/ \
	./RTX2001A/test/test_mb.c ./RTX2001A/test/scp_stub.c ../Unity/src/unity.c \
	-L/opt/local/lib -lpthread -lpcre -L/opt/local/lib/ -lpng -lz   \
	./RTX2001A/rtx2001a.a \
	-o BIN/test_mb

$ ./BIN/test_mb
./RTX2001A/test/test_mb.c:55:test_long_store_00:FAIL: Expected 0 Was 64

-----------------------
1 Tests 1 Failures 0 Ignored
FAIL

mb is Memory Bus
scp_stub.c is scp without main()
Building on Unity unit testing framework.

FFI integration proceeding apace. This means that the Rust bindgen tool has digested simh/sim_defs.h

Running /Users/jeffreychimene/git/SIM2001A/target/debug/deps/SIM2001A-8257d75b9163b925

running 101 tests
test bindgen_test_layout_BITFIELD … ok
<…>
test tests::it_works … ok

20-Aug
So no-std bindgen is out. Turns out bindgen relies on std:: for its work. Rethinking the integration piece

20-Aug
Integration with simh looks like it will confined to using the FFI to call into Rust from the simh public API.

This is the time to thank Phil Koopman, PJK, for his trailblazing work documenting the RTX2001A. This project would not be possible without his work on the RTX2000 simulator.

Implementation

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Makefile integration via  cargo build

bindgen for FFI bindings

arrayVec for RAM allocation

The RTX_2000 simulator from Phil Koopman has the instruction decoding logic. It also nicely integrates the zero-cycle “;” word.

Use Rust’s “no-std” feature flag. After all, this is an embedded system. SIMH provides virtual file I/O, debugging support, virtual console, virtual display.

See if instruction decoding can be accomplished via Rust’s enum type.

Rust’s Borrow Checker will verify memory read/write access.

Rust’s array slices should be useful.

You fill in sim_instr do the instruction decoding and execution.
sim_load will typically take some input file and put it in memory.
cpu_reg should contain all machine state.
parse_sym/fprint_sym is to assemble (with DEPOSIT) and disassemble (EXAMINE-M) instructions.
sim_devices is an array of DEVICE * for peripherals. Something like
build_dev_tab will go through the array and initialize data structures
at run time.
Refer to this: simh doc
Make use of asynchronous events. sim_activate posts a future event.
The “svc” routine will be called.

sub/readme.txt

parse_sym invokes Forth interpreter
print_sym invokes Forth disassembler

Build with SIM_ASYNCH_IO=0

Bus Interfaces

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ASIC Bus Interface
Memory Interface
Return Stack Bus
Parameter Stack Bus

RTX Reprints, pg. 8

Callouts note bus assignments. Buses can be active in parallel. Instruction timings are related to this implementation. Threads are independent of each other.

Design

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#![no_std] is a crate-level attribute that indicates that the crate will link to the core-crate instead of the std-crate. The libcore crate in turn is a platform-agnostic subset of the std crate which makes no assumptions about the system the program will run on. As such, it provides APIs for language primitives like floats, strings and slices, as well as APIs that expose processor features like atomic operations and SIMD instructions. However it lacks APIs for anything that involves platform integration. Because of these properties no_std and libcore code can be used for any kind of bootstrapping (stage 0) code like bootloaders, firmware or kernels.

Embedded Rust

The RTX 2000 instruction set is sub-divided into six instruction classes, with each section controlling a hardware operation.

RTX88 Concepts, pg. 6
  • Consider implementing instruction classes as traits

Microcontrollers have on-chip support hardware for performing many of the functions typically needed in a real-time system, including an interrupt controller, a memory page controller, two stack controllers, and three 16-bit counter/timers. In addition to these “on-chip peripherals”, the RTX 2000 provides a 16-by-16 hardware multiplier, while the RTX 2010 provides a 16-by-16 hardware multiplier-accumulator along with a 32- bit Barrel Shifter and a 32-bit Leading Zero Detector for Floating Point support.

RTX2000 Family Programmer’s Reference Manual, pg. 3

harris rtx2000
In byte/word addressing the RTX-2000/2010 is really fine:
E.g.    HEX CREATE X 12 C, 34 C,
1. If you fetch 16 bits from an *even* address you’ll get hi,lo
2. If you fetch 16 bits from *odd* address your value will be *swapped*
3. Of course the RTX2000/2010 also fetches and stores 8-bit characters
   (by hardware, without software tricks)
The only think you have to watch for is that 16-bit variables
are created at even addresses, if you mix 16/8 bit storage:
        HEX CREATE Y
                12 C, 3456 , 789A ,
Regards,
Rolf.
http://computer-programming-forum.com/22-forth/404289809b102941-2.htm, 25 / 28

Four separate buses for 1he data stack, return stack, memory and ASIC Bus and operate in parallel, significantly increasing instruction execution efficiency.

RTX88 Concepts, pg. 6
  • Consider implementing buses as cooperating threads
  • Use simh debugger support classes to cause breakpoints at action points.

The instructions >R, octal 157201, and R>, octal 147321, are of special interests as shown in Figure 3.8. The data stack and the return stack in NC4000 can be viewed as a 515 cell register array, with the I, T, and N registers at the center. The entire array can be shifted to the left by >R and to the right by R>. The three registers at the center of this large array is a window by which ALU has access to the array.

Footsteps, pg. 42
  • array slice

As is evident from the step math instruction format, there. are ten bits, not including the Return bit, that determine step math operation, which implies that there are 1024 possible step math operations. While this is true, not all of these operations are useful.

RTX88, pg. 230
  • Consider math instructions in a later revision

Implement dispatch a la VAX. CISC machine implementations seem to benefit from this design.

In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base.  This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consistently throughout the VM.  Many existing VM’s count time in instructions, some count time in cycles that may align with cycles in the original hardware that may reflect different instructions and/or combinations of memory references.

simh controller doc, pg. 6

timebase will be Instruction count. All instructions execute in one or two cycles. Cycle count cannot be used to increment the close. Instructions per cycle is either 1 or 2.

A bus cycle starts at clock half-cycle rising edge.

Bus Traits
Use these traits to statically ensure data of correct width is transferred on that bus

  • ASIC bus data transfer
    • A
    • Three-bit bus
  • Memory bus data transfer
    • M

This is a 19-bit bus, along with Upper Data Strobe (UDS) and Lower Data Strobe (LDS), which allows the RTX to address 1 megabyte of memory.

RTX2000 Family Programmer’s Reference Manual, pg. 13
  • Parameter stack bus data transfer
    • P
    • 16-bit bus
  • Return stack bus data transfer
    • R
    • 16-bit bus

Bus Implementation

  • READ
    • Read
      • M,P,R
    • ReadIO
      • A
  • WRITE
    • Write
      • M,P,R
    • WriteIO
      • A
  • ERROR
    • A,M,P,R

Bus Signals

  • DATAI
  • DATAO
  • CLK
    Derived from CLKI/2

Each instruction will trigger the appropriate bus activity during instruction execution

Q: How does a bus know the current cycle. CLKI/2 signal?
A: Clock routine will broadcast current tick to each bus.

All I/O is synchronous

Admonitions

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Using bit 15 to encode a subroutine call has only one drawback–it can only call subroutines in the lower 32K word in the main memory. The upper 32K word addressable memory cannot be used to store executable programs. This was a very serious trade-off in the design of NC4000. The most important argument to justify this trade-off is that Forth programs written for NC4000 can be extremely compact due to the single cycle subroutine calls and the condensation of many Forth words into a single instruction. Many large programs are needed to fill up the 32K word program space. By the time memory requirements exceed 32K words, you will probably have a 32 bit Novix chip to accommodate these stupendous programs resulting from the lazy-minded or uncommunicative programming teams.

Footsteps, pg. 23

This model only approximates the functioning of NC4000, because NC4000 was designed not based on this kind of models, but by a large set of logic equations compiled into gate array patterns. Many special functions in NC4000 are impossible to represent in simple graphical models.

Footsteps, pg. 34

Instruction execution is actually the least complicated part of the design; memory and I/O organization should be tackled first.

simh controller doc, pg. 7

: MAX ( n1 n2 -- n1 ; n2 )
OVER OVER -               n1 - n2 0< IF
BEGIN SWAP DROP           n1 < n2, drop n1. Otherwise, jump
                          to THEN in MIN and drop n2.
;

: MIN ( n1 n2 -- n1 ; n2 )
OVER OVER -               n1 - n2
0<
UNTIL                     n1 > n2, jump to BEGIN in MAX and drop n1.
THEN DROP                 Otherwise, drop n1.
;

The funny IF-BEGIN… UNTIL-THEN structure spanning over two definitions
MAX and MIN lets two definitions executing two alternate pieces of code,
SWAP DROP or DROP. Chuck can do tricks like this because cmForth does
not have compiler security and protection. Not recommended for general
programming practice.

Footsteps, pg. 63

Co-routines on steroids. If this were conventional assembler, we’d never notice. Crossing into compilation adds another dimension.