simh

Makefile integration via  cargo build

bindgen for FFI bindings

arrayVec for RAM allocation

The RTX_2000 simulator from Phil Koopman has the instruction decoding logic. It also nicely integrates the zero-cycle “;” word.

Use Rust’s “no-std” feature flag. After all, this is an embedded system. SIMH provides virtual file I/O, debugging support, virtual console, virtual display.

See if instruction decoding can be accomplished via Rust’s enum type.

Rust’s Borrow Checker will verify memory read/write access.

Rust’s array slices should be useful.

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You fill in sim_instr do the instruction decoding and execution.
sim_load will typically take some input file and put it in memory.
cpu_reg should contain all machine state.
parse_sym/fprint_sym is to assemble (with DEPOSIT) and disassemble (EXAMINE-M) instructions.
sim_devices is an array of DEVICE * for peripherals. Something like
build_dev_tab will go through the array and initialize data structures
at run time.
Refer to this: simh doc
Make use of asynchronous events. sim_activate posts a future event.
The “svc” routine will be called.

sub/readme.txt

parse_sym invokes Forth interpreter
print_sym invokes Forth disassembler

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Build with SIM_ASYNCH_IO=0

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• Control Inputs
  • Clock
  • Configuration Control
• Timer Inputs
  • Timer/Counters
• Interrupt Inputs
  • Interrupt Control

Stack Controllers
Interrupt Controller
Math Support
Counter/Timers

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#![no_std] is a crate-level attribute that indicates that the crate will link to the core-crate instead of the std-crate. The libcore crate in turn is a platform-agnostic subset of the std crate which makes no assumptions about the system the program will run on. As such, it provides APIs for language primitives like floats, strings and slices, as well as APIs that expose processor features like atomic operations and SIMD instructions. However it lacks APIs for anything that involves platform integration. Because of these properties no_std and libcore code can be used for any kind of bootstrapping (stage 0) code like bootloaders, firmware or kernels.

Embedded Rust

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The RTX 2000 instruction set is sub-divided into six instruction classes, with each section controlling a hardware operation.

RTX88 Concepts, pg. 6

• Consider implementing instruction classes as traits

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Microcontrollers have on-chip support hardware for performing many of the functions typically needed in a real-time system, including an interrupt controller, a memory page controller, two stack controllers, and three 16-bit counter/timers. In addition to these “on-chip peripherals”, the RTX 2000 provides a 16-by-16 hardware multiplier, while the RTX 2010 provides a 16-by-16 hardware multiplier-accumulator along with a 32- bit Barrel Shifter and a 32-bit Leading Zero Detector for Floating Point support.

RTX2000 Family Programmer’s Reference Manual, pg. 3

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harris rtx2000
In byte/word addressing the RTX-2000/2010 is really fine:
E.g.    HEX CREATE X 12 C, 34 C,
1. If you fetch 16 bits from an *even* address you’ll get hi,lo
2. If you fetch 16 bits from *odd* address your value will be *swapped*
3. Of course the RTX2000/2010 also fetches and stores 8-bit characters
   (by hardware, without software tricks)
The only think you have to watch for is that 16-bit variables
are created at even addresses, if you mix 16/8 bit storage:
        HEX CREATE Y
                12 C, 3456 , 789A ,
Regards,
Rolf.
http://computer-programming-forum.com/22-forth/404289809b102941-2.htm, 25 / 28

Four separate buses for 1he data stack, return stack, memory and ASIC Bus and operate in parallel, significantly increasing instruction execution efficiency.

RTX88 Concepts, pg. 6

• Consider implementing buses as cooperating threads
• Use simh debugger support classes to cause breakpoints at action points.

The instructions >R, octal 157201, and R>, octal 147321, are of special interests as shown in Figure 3.8. The data stack and the return stack in NC4000 can be viewed as a 515 cell register array, with the I, T, and N registers at the center. The entire array can be shifted to the left by >R and to the right by R>. The three registers at the center of this large array is a window by which ALU has access to the array.

Footsteps, pg. 42

• array slice

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As is evident from the step math instruction format, there. are ten bits, not including the Return bit, that determine step math operation, which implies that there are 1024 possible step math operations. While this is true, not all of these operations are useful.

RTX88, pg. 230

• Consider math instructions in a later revision

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Implement dispatch a la VAX. CISC machine implementations seem to benefit from this design.

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In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base.  This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consistently throughout the VM.  Many existing VM’s count time in instructions, some count time in cycles that may align with cycles in the original hardware that may reflect different instructions and/or combinations of memory references.

simh controller doc, pg. 6

timebase will be Instruction count. All instructions execute in one or two cycles. Cycle count cannot be used to increment the close. Instructions per cycle is either 1 or 2.

A bus cycle starts at clock half-cycle rising edge.

Bus Traits
Use these traits to statically ensure data of correct width is transferred on that bus

• ASIC bus data transfer
  • A
  • Three-bit bus

• Memory bus data transfer
  • M

This is a 19-bit bus, along with Upper Data Strobe (UDS) and Lower Data Strobe (LDS), which allows the RTX to address 1 megabyte of memory.

RTX2000 Family Programmer’s Reference Manual, pg. 13

• Parameter stack bus data transfer
  • P
  • 16-bit bus
• Return stack bus data transfer
  • R
  • 16-bit bus

Bus Implementation

• READ
  • Read
    • M,P,R
  • ReadIO
    • A
• WRITE
  • Write
    • M,P,R
  • WriteIO
    • A
• ERROR
  • A,M,P,R

Bus Signals

• DATAI
• DATAO
• CLK
  Derived from CLKI/2

Each instruction will trigger the appropriate bus activity during instruction execution

Q: How does a bus know the current cycle. CLKI/2 signal?
A: Clock routine will broadcast current tick to each bus.

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All I/O is synchronous

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It is also important to understand NC4000 instruction set in order to study the code in cmForth, a piece of art in software by the master himself.

Footsteps, pg. 22

First thing I always ask is what software is available?

private communication

Let’s try the AppForth image from the rtx2000_simulator on github